101 lines
3.0 KiB
C
101 lines
3.0 KiB
C
/* RISC-V 'V' Extension intrinsics include file.
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Copyright (C) 2022-2023 Free Software Foundation, Inc.
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This file is part of GCC.
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GCC is free software; you can redistribute it and/or modify it
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under the terms of the GNU General Public License as published
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by the Free Software Foundation; either version 3, or (at your
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option) any later version.
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GCC is distributed in the hope that it will be useful, but WITHOUT
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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License for more details.
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Under Section 7 of GPL version 3, you are granted additional
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permissions described in the GCC Runtime Library Exception, version
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3.1, as published by the Free Software Foundation.
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You should have received a copy of the GNU General Public License and
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a copy of the GCC Runtime Library Exception along with this program;
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see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
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<http://www.gnu.org/licenses/>. */
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#ifndef __RISCV_VECTOR_H
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#define __RISCV_VECTOR_H
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#include <stdint.h>
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#include <stddef.h>
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#ifndef __riscv_vector
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#error "Vector intrinsics require the vector extension."
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#else
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#ifdef __cplusplus
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extern "C" {
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#endif
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enum RVV_CSR {
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RVV_VSTART = 0,
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RVV_VXSAT,
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RVV_VXRM,
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RVV_VCSR,
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};
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__extension__ extern __inline unsigned long
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__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
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vread_csr(enum RVV_CSR csr)
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{
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unsigned long rv = 0;
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switch (csr)
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{
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case RVV_VSTART:
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__asm__ __volatile__ ("csrr\t%0,vstart" : "=r"(rv) : : "memory");
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break;
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case RVV_VXSAT:
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__asm__ __volatile__ ("csrr\t%0,vxsat" : "=r"(rv) : : "memory");
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break;
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case RVV_VXRM:
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__asm__ __volatile__ ("csrr\t%0,vxrm" : "=r"(rv) : : "memory");
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break;
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case RVV_VCSR:
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__asm__ __volatile__ ("csrr\t%0,vcsr" : "=r"(rv) : : "memory");
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break;
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}
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return rv;
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}
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__extension__ extern __inline void
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__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
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vwrite_csr(enum RVV_CSR csr, unsigned long value)
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{
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switch (csr)
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{
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case RVV_VSTART:
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__asm__ __volatile__ ("csrw\tvstart,%z0" : : "rJ"(value) : "memory");
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break;
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case RVV_VXSAT:
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__asm__ __volatile__ ("csrw\tvxsat,%z0" : : "rJ"(value) : "memory");
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break;
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case RVV_VXRM:
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__asm__ __volatile__ ("csrw\tvxrm,%z0" : : "rJ"(value) : "memory");
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break;
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case RVV_VCSR:
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__asm__ __volatile__ ("csrw\tvcsr,%z0" : : "rJ"(value) : "memory");
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break;
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}
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}
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/* NOTE: This implementation of riscv_vector.h is intentionally short. It does
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not define the RVV types and intrinsic functions directly in C and C++
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code, but instead uses the following pragma to tell GCC to insert the
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necessary type and function definitions itself. The net effect is the
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same, and the file is a complete implementation of riscv_vector.h. */
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#pragma riscv intrinsic "vector"
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#ifdef __cplusplus
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}
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#endif // __cplusplus
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#endif // __riscv_vector
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#endif // __RISCV_VECTOR_H
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